Polycrystalline silicon and polycides are used widely as gate materials in MOS LSI technology. The modern trend with respect to such technology, is to go to greater and greater device densities which in turn necessitates smaller minimum feature sizes and smaller separations in VLSI integrated circuits. In order to achieve these increasingly small feature sizes and separations, the lithographic pattern-transfer process must be very precise. In particular, the minimum mask dimensions that are available for a specific lithographic process substantially determines the minimum feature size and the minimum feature separation. These minimum feature sizes and separations are also dependent upon the degree of feature size change that typically occurs with a particular processing step. For example, an isotropic etching step used in the fabrication of a polysilicon gate: may produce a gate with sloping or undercut walls. Such a gate configuration would not at all be close to the lithographic gate feature size.
Hence, feature size change depends greatly upon the pattern-transfer process. Anisotropic dry etching techniques minimize feature size changes. Such techniques are required because lateral device dimensions in modern ICs are being scaled down typically below approximately 2 um while the thicknesses of the films are being scaled down less rapidly. If patterning is performed by isotropic wet or isotropic plasma etching techniques, substantial reductions in feature size including undercutting, linewidth reductions and even total loss of the etched pattern can occur.
As earlier stated, anisotropic etching techniques avoid these problems. One such technique known as plasma etching, employs a plasma coupled with an RF voltage to create a chemically active etchant that forms a volatile etching product with the unprotected layers of a substrate. This technique is made possible by the existence of suitable combinations of substrate and etching gas. Such combinations are available for the majority of the films used to fabricate semiconductor devices.
Another technique known as reactive ion etching is very similar to plasma etching and essentially differs by the operational pressures and voltages at which the equipments, used in theses processes, are operated. More specifically, RIE operates at lower pressures (approximately 10.sup.-2 Torr) than plasma etching and is thus, somewhat more directional.
Examples of typical etching gases include chlorine and fluorine compounds which are respectively available in the form of CCl.sub.4 and CF.sub.4. These compounds have been adapted for etching polysilicon, SiO.sub.2 Si.sub.3 N.sub.4, and metals. For example, fluorine radicals will react with silicon to produce a volatile silicon tetrafluoride etching product.
Oxygen containing plasmas are also employed and can be used to etch organic films including resist. Further, the etching rate of the plasma can be substantially increased by adding small percentages of O.sub.2 (5-10%) to the etch gas.
Dry etching techniques, however, have etching selectivity problems. In particular, selectivity is required to pattern polysilicon gate electrodes without removing the thin underlying gate oxide, since the etching ratios needed increases in both instances as the devices become smaller. More specifically, a higher degree of selectivity for silicon dioxide relative to silicon is needed because the junction depth decreases faster than the thickness of the field oxide. Further, a higher degree of selectivity for silicon relative to silicon dioxide is a must because the thickness of the gate oxide decreases at a faster rate than the thickness of the gate electrode. Additionally, the required selectivity depends on the thicknesses of the etched and underlying films as well as on the topography produced by earlier processing steps.
Etching of gate stacks is usually performed in some type of single wafer reactor system. The reactor typically employs a top inductive coil and the bottom electrode is capacitively coupled. The coil is attached around or on top of the outside of the reactor and operate to inductively couple the rf voltage into the plasma. A pump is connected to the reactor and operates to evacuate the reactor. When RF energy is applied to the coil and to the electrode, the gas fed into the reactor is converted to a plasma.
Prior art processes for etching submicron polysilicon/polycide gate stacks on LAM-TCP employ high inductive coil power. In a typical prior art process for an OBERON gate stack etch in LAM-TCP, the top coil power is commonly adjusted to between 300 and 600 watts. The bottom electrode power is usually adjusted to between 75 and 300 watts. Chlorine, nitrogen and oxygen are employed as the etching gases. The purpose of the high top coil power is to generate high density plasma at low pressures. Such pressures are on the order of less than 10 milli-Torr. High top coil powers are employed in theses prior art etching techniques because it is a commonly held belief in the art that high plasma density is necessary to achieve adequate etch rates at low pressures. It is also commonly held belief in the art that such plasmas cause relatively little damage due to the lower kinetic energy of the ions generated in these plasmas.
The high coil powers, however, generate non-uniform plasmas which causes charging damage. Further, the high coil powers can reduce the selectivities to the gate oxide because of the high ion density. High ion density is also associated with high radical density. This can create problems because the radicals can undercut the layer being etched and/or generate a notch at the foot of the gate stack. In order to alleviate the undercut or notching, more side wall passivation is needed which can lead to undesirably large critical dimension (CD) changes.
It is therefore, a primary object of the present invention to provide a low power process for etching polysilicon/polycide gate stacks for DRAM applications.